发明名称 Implementation of double data rate embedded memory in programmable devices
摘要 A memory block of a programmable device uses a double data rate communication scheme to communicate data with logic cells at a rate of two bits per clock cycle per data line. The memory block can be configured to use the double data rate communication scheme or a single data rate communication scheme. The memory block can switch between either communications scheme as needed to communicate with different portions of the programmable device. If a memory block of a programmable device includes two or more data access ports, an embodiment of a programmable device allows each data access port to be configured for single data rate or double data rate communications independently of other data ports. Any arbitrary logic cell of the programmable device can communicate with a memory block using the double data rate communication scheme by configuring additional logic cells to operate as a double data rate interface.
申请公布号 US7460431(B1) 申请公布日期 2008.12.02
申请号 US20050242693 申请日期 2005.10.03
申请人 发明人
分类号 G11C8/00 主分类号 G11C8/00
代理机构 代理人
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