| 摘要 |
A synchronous clock generation apparatus including a multiplier for multiplying a horizontal synchronizing signal by a horizontal synchronizing pulse signal to generate multiplication data, a gain variable digital LPF for extracting only DC components from the multiplication data and capable of performing gain adjustment, and a controller for calculating gain adjustment data, lock center frequency setting data, and LPF gain adjustment data based on the correction data. The controller detects an amount of deviation from the lock center frequency and an amount of variation, displaces the lock center frequency and shifts the lock range along the frequency axis to enlarge the apparent lock range when the amount of deviation is large, and reduces the gain to improve lock precision when the amount of variation is small, without expanding bits in the circuit configuration.
|
