发明名称 Deferred branch history update scheme
摘要 In one embodiment, a processor comprises a branch prediction array, an index generator coupled to the branch prediction array, and a control unit coupled to the index generator. The branch prediction array is configured to store a plurality of branch predictions for conditional branches. The index generator is configured to generate an index to the branch prediction array responsive to at least a portion of a fetch address corresponding to a fetch request that is at a first pipeline stage of the processor and further responsive to a branch history. The control unit is configured to update the branch history responsive to a first fetch request at the first pipeline stage and to defer the update for a second fetch request to a second pipeline stage subsequent to the first pipeline stage.
申请公布号 US7461243(B2) 申请公布日期 2008.12.02
申请号 US20050316722 申请日期 2005.12.22
申请人 SUN MICROSYSTEMS, INC. 发明人 ALI ABID;LU JIEJUN;KEISH BRIAN F.
分类号 G06F7/38;G06F9/00;G06F9/44;G06F15/00 主分类号 G06F7/38
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