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发明名称
感测架构
摘要
本发明揭示了一种记忆体系统。在一实施例中,该记忆体系统包括第一位元线,其中该第一位元线产生第一暂态电流。该记忆体系统还包括耦合至该第一位元线之一感测放大器。该记忆体系统还包括耦合至该感测放大器之第二位元线,其中该第二位元线产生等于第一暂态电流之第二暂态电流。该感测放大器可使第一及第二暂态电流被抵销。根据此处所揭示之系统,无需受暂态电流之不利影响的情况下就可确定一记忆体单元之状态。
申请公布号
TW200847172
申请公布日期
2008.12.01
申请号
TW097101298
申请日期
2008.01.11
申请人
爱特梅尔公司
发明人
盖布利尔 贝里;罗伦佐 贝德瑞达;赛蒙 巴尔特利;吉奥吉奥 波西西欧
分类号
G11C16/28(2006.01)
主分类号
G11C16/28(2006.01)
代理机构
代理人
陈长文
主权项
地址
美国
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