| 摘要 |
<p>AN ON-CHIP CAPACITOR HAVING PLURALITY OF CAPACITOR LAYERS@EACH CAPACITOR LAYER COMPRISING A PAIR OF FRAMES, SUCH THAT A FIRST FRAME OF THE PAIR IS ELECTRICALLY CONNECTED TO FIRST FRAMES ON EACH OTHER CAPACITOR LAYER AND A SECOND FRAME OF THE PAIR IS ELECTRICALLY CONNECTED TO SECOND FRAMES ON EACH OTHER CAPACITOR LAYER; A PLURALITY OF TINES PROJECTING FROM EACH FRAME WITHIN THE RESPECTIVE CAPACITOR LAYER, THE TINES FROM EACH FRAME MESHING SO AS TO FORM AN ARRAY OF SEQUENTIALLY ALTERNATING TINES FROM EACH FRAME TO PROVIDE A LAYER CAPACITANCE WITHIN THE CAPACITOR LAYER, WHEREIN THEMULTI-LAYER CAPACITOR FURTHER INCLUDES A PLURALITY OF PROJECTIONS FROM SAID TINES, SAID PROJECTIONS EXTENDING BETWEEN FRAMES OF ADJACENT CAPACITOR LAYERS SO AS TO PROVIDE AN INTERSTITIAL CAPACITANCE BETWEEN THE CAPACITOR LAYERS, WHEREIN THE TOTAL CAPACITANCE OF THE ON-CHIP CAPACITOR IN THE SUM OF EACH LAYER CAPACITANCE AND EACH INTERSTITIAL CAPACITANCE.</p> |
