Watchdog system and method for monitoring functionality of a processor

摘要

A watchdog system for monitoring functionality of a processor is disclosed. The system comprises control logic having N number of acknowledgement signal inputs. The system also comprises a first timer, a second timer; a third timer, and a reset signal generator. The first timer is started upon boot up of the watchdog system. The second and third timers are started upon receiving a first acknowledgement signal at one of said N number of acknowledgement signal inputs. The reset signal generator generates a reset signal if any one of three conditions is met. The first condition is that no acknowledgement signal was received at one of the N number of acknowledgement signal inputs before the expiration of the first timer. The second condition is that an acknowledgement signal is received at one of the N number of acknowledgement signal inputs before the expiration of the second timer. The third condition is that an acknowledgement signal was not received at all the N number of acknowledgement signal inputs before the expiration of the third timer.