DISTRIBUTED LOOP CONTROLLER ARCHITECTURE FOR MULTI-THREADING IN UNI-THREADED PROCESSORS

摘要

In one aspect, a virtually multi-threaded distributed instruction memory hierarchy that can support the execution of multiple incompatible loops in parallel is disclosed. In addition to regular loops, irregular loops with conditional constructs and nested loops can be mapped. The loop buffers are clustered, each loop buffer having its own local controller, and each local controller is responsible for indexing and regulating accesses to its loop buffer.