DYNAMIC PROCESSOR POWER MANAGEMENT DEVICE AND METHOD THEREOF

摘要

A processor (105) can operate in different power modes. In an active power mode, the processor executes software (303). In response to receiving a halt indication (304) from the software, hardware at the processor evaluates bus transactions (306) for the processor. If the bus transactions meet a heuristic (307), hardware places a processor core in a lower power mode, such as a retention mode (308). Because the bus transactions are evaluated by hardware, rather than by software, and the software is not required to perform handshakes and other protocols to place the processor in the lower power mode, the processor is able to place the processor core into the lower power mode more quickly, thereby conserving power.