发明名称 Cache memory storing validity data and control data for the cached data, such that the control data can be modified by the attached processor.
摘要 A data processing system is provided with at least one processor 4, 6, a main memory 18 and a cache memory 14. Cache data within the cache memory 14 has validity data V and control data associated with it. The control data controls access to the cached data. Program instructions executed by the processors 4, 6 control a cache controller 26 to modify the control data associated with the cached data whilst it remains stored within the cache memory 14 and remains valid. The control data may, specify a security flag indicating whether access is restricted to secure processes or processors. The control data may be TAG data and/or program thread specifying data. The processors may have different access states and the main memory may have a controlled region which is accessible only by a processor running in an authorised access state. The control data in the cache may mark cached data as controlled data cached by a processor in an authorised access state to be accessed only by that processor. The processor may change the control data if the access status of the data is changed.
申请公布号 GB2449454(A) 申请公布日期 2008.11.26
申请号 GB20070009817 申请日期 2007.05.22
申请人 ARM LIMITED 发明人 PETER WILLIAM HARRIS;DONALD FELTON
分类号 G06F12/08;G06F12/12 主分类号 G06F12/08
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