发明名称
摘要 <p>PROBLEM TO BE SOLVED: To protect the outputting state of an output port though a reset signal coming from a reset circuit comes to an unscheduled reset level. SOLUTION: The reset signal coming from the reset circuit 165 having a reset IC 651 is inputted to the reset terminals of a CPU 101 for display control and a VDP 103. A port reset signal is supplied from the output port of the CPU 101 to the reset terminals of an I/O expanders 171 to 173. In initialization processing, the CPU 101 raises the level of the port reset signal from a low level (reset level) to a high level. When it is detected that starting is based on a reset signal which is not a normal reset signal in the initialization processing, the CPU 101 never make the level of the port reset signal low.</p>
申请公布号 JP4187950(B2) 申请公布日期 2008.11.26
申请号 JP20010205365 申请日期 2001.07.05
申请人 发明人
分类号 A63F7/02 主分类号 A63F7/02
代理机构 代理人
主权项
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