发明名称 |
Structure for transistor devices in an SRAM cell |
摘要 |
An SRAM memory cell having first and second transfer gate transistors. The first transfer gate transistor includes a first source/drain connected to a bit line and the second transfer gate transistor has a first source/drain connected to a complement bit line. Each transfer gate transistor has a gate connected to a word line. The SRAM memory cell also includes first and second pull-down transistors configured as a storage latch. The first pull-down transistor has a first source/drain connected to a second source/drain of said first transfer gate transistor; the second pull-down transistor has a first source/drain connected to a second source/drain of said second transfer gate transistor. Both first and second pull-down transistors have a second source/drain connected to a power supply voltage node. The first and second transfer gate transistors each include a gate oxide layer having a first thickness, and the first and second pull-down transistors each include a gate oxide layer having a second thickness, wherein and the first thickness is different from the second thickness.
|
申请公布号 |
USRE40579(E1) |
申请公布日期 |
2008.11.25 |
申请号 |
US20000694051 |
申请日期 |
2000.10.20 |
申请人 |
STMICROELECTRONICS, INC. |
发明人 |
BRYANT FRANK RANDOLPH;CHAN TSIU CHIU |
分类号 |
H01L29/76;H01L29/94;H01L31/00 |
主分类号 |
H01L29/76 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|