发明名称 Dielectric relaxation memory
摘要 A capacitor structure having a dielectric layer disposed between two conductive electrodes, wherein the dielectric layer contains at least one charge trap site corresponding to a specific energy state. The energy states may be used to distinguish memory states for the capacitor structure, allowing the invention to be used as a memory device. A method of forming the trap cites involves an atomic layer deposition of a material at pre-determined areas in the dielectric layer.
申请公布号 US7457184(B2) 申请公布日期 2008.11.25
申请号 US20060389150 申请日期 2006.03.27
申请人 MICRON TECHNOLOGY, INC. 发明人 BASCERI CEM;SANDHU GURTEJ
分类号 G11C7/00;G11C11/24;G11C11/34;H01L29/76 主分类号 G11C7/00
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