发明名称 Open drain output circuit
摘要 An open drain output circuit for use as an I<SUP>2</SUP>C bus interface. The open drain output circuit includes an output terminal. An input unit performs a first operation causing the potential at the output node to steeply fall and a second operation for gradually raising the potential in accordance with transition of an input signal. An output transistor connected to the output node of the input unit and the output terminal is turned OFF in the first operation and turned ON in the second operation. A delay time adjustment circuit reduces the difference between a delay time from transition of the input signal until when the output transistor is turned OFF in the first operation and a delay time from transition of the input signal until when the output transistor is turned ON in the second operation.
申请公布号 US7456649(B2) 申请公布日期 2008.11.25
申请号 US20060633454 申请日期 2006.12.05
申请人 FUJITSU LIMITED 发明人 MIYAZAKI HIROSHI
分类号 H03K17/16;H03K19/003 主分类号 H03K17/16
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