| 摘要 |
A pulse width modulation circuit 1 of the present invention changes the voltage of a first integration circuit C 1 during the first period T 1 of the clock signal MCLK based on a current based on an audio signal eS, changes the voltage of the first integration circuit C 1 based on a constant bias current in the opposite direction while changing the voltage of a second integration circuit C 2 during the second period T 2 , and changes the voltage of the second integration circuit C 2 based on the bias current during the third period T 3 . The amount of time from the start of the second period T 2 until the voltage of the first integration circuit C 1 reaches the reference voltage Vth is detected, and the amount of time from the start of the third period T 3 until the voltage of the second integration circuit C 2 reaches the reference voltage Vth is detected. The voltage of the first integration circuit C 1 is kept at the reference voltage Vth from when the voltage of the first integration circuit C 1 reaches the reference voltage Vth until the start of the third period T 3 , and the voltage of the second integration circuit C 2 is kept at the reference voltage Vth from when the voltage of the second integration circuit C 2 reaches the reference voltage Vth until the start of the fourth period T 4 . A pulse signal is generated, in which the pulse widths are equal to the amounts of time required for first and second integration circuits C 1 and C 2 to reach the reference voltage Vth.
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