发明名称 |
Semiconductor memory device, system and method of testing same |
摘要 |
A semiconductor memory device includes a plurality of address pads, a plurality of DQ pads, an address buffer, a data input buffer, a latch circuit and a first delay circuit. The address buffer receives a plurality of first address signals through the address pads and buffers the first address signals to generate a plurality of second address signals. The data input buffer receives one of a plurality of input data through the DQ pads and buffers the input data to generate a first data or receives the first address signals through the DQ pads and buffers the address signals to generate a plurality of third address signals. The latch circuit latches the third address signals to generate fourth address signals in response to a test mode control signal. The first delay circuit selects the second address signals or the fourth address signals and delays the selected address signals for a predetermined time to generate fifth address signals.
|
申请公布号 |
US7457179(B2) |
申请公布日期 |
2008.11.25 |
申请号 |
US20070620096 |
申请日期 |
2007.01.05 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
CHEON KWUN-SOO |
分类号 |
G11C7/00;G11C7/10;G11C8/00;G11C29/00 |
主分类号 |
G11C7/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|