发明名称 |
Distributed delay-locked-based clock and data recovery systems |
摘要 |
A clock and data recovery system using a distributed variable delay line is provided. The clock and data recovery system can use a delay-locked loop methodology to align a local clock with an incoming data stream. The variable delay line can include a transmission line coupled with a plurality of variable capacitors responsive to a control voltage. The variable delay line can also have a ladder configuration of multiple LC subcircuits each having a variable impedance responsive to a control voltage.
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申请公布号 |
US7456670(B2) |
申请公布日期 |
2008.11.25 |
申请号 |
US20060382807 |
申请日期 |
2006.05.11 |
申请人 |
THE REGENTS OF THE UNIVERSITY OF CALIFORNIA |
发明人 |
MAHANAVELU RAVINDRAN;HEYDARI PAYAM |
分类号 |
H03H11/26;H02M3/07;H03K3/356;H03K5/00;H03K5/145;H03K19/21;H03L7/081;H03L7/085;H03L7/089;H04L7/033 |
主分类号 |
H03H11/26 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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