| 摘要 |
A phase-locked loop and a driving method thereof implement a fast circuit operation by reducing a locking time consumed when generating an internal clock of a required frequency. A phase frequency detection unit(510) detects the phase difference between a reference clock(CLK REF) and a feedback clock(CLK FED) and outputs the detection signal corresponding to the detected phase difference. A control voltage generator generates the control voltage having the voltage level corresponding to the detection signal. A voltage control oscillation unit(550) generates an internal clock having a frequency corresponding to a level of a control voltage. A start-up driving unit(590) drives a control voltage stage in a predetermined start-up level before the voltage control oscillation unit is activated by responding to the start up level multiplex signal corresponding to the frequency of the reference clock. |
