发明名称 SEMICONDUCTOR DEVICE AND METHOD OF MEASURING SHEET RESISITANCE OF LOWER LAYER CONDUCTIVE PATTERN THEREOF
摘要 Contact holes (openings) ( 17 ) are created in the upper electrode ( 14 ) and the dielectric film ( 15 ) of a polysilicon-insulator-polysilicon (PIP) capacitive element to form a plurality of evaluation patterns wherein the lower electrode ( 13 ) and upper layer wiring lines ( 20 ) for measurement are electrically connected through contacts ( 16 ). At least four evaluation patterns are created by a combination of two or more values of a distance L with different values of a width W. Since it can be assumed that a difference in the resistance value between the respective evaluation patterns is only due to the effect of a change in a rectangular region (W*L) between the contact holes (openings) ( 17 ), it is possible to easily calculate the sheet resistance of the high-resistance portion from a change in the resistance value of each of the measurement patterns.
申请公布号 US2008284452(A1) 申请公布日期 2008.11.20
申请号 US20070838252 申请日期 2007.08.14
申请人 NEC ELECTRONICS CORPORATION 发明人 SAKAMOTO HIDEO
分类号 G01R31/26;H01L23/58 主分类号 G01R31/26
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