| 摘要 |
An image processing controller performs transmission and processing of image data by connecting an engine and a CPU connected via a chipset. A first controller controls communication with the chipset via a first PCI-Express I/F. A second controller controls communication with the engine when it is connected via a second PCI-Express I/F. A third controller controls communication with the engine when it is connected via a PCI I/F. The first controller receives, on behalf of the engine, an access from the CPU to the engine and inhibits a reference by the CPU to a resource connected to the image processing controller.
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