发明名称 |
INTERFACE BOARD, SIMULATOR, SYNCHRONIZATION METHOD AND SYNCHRONIZATION PROGRAM |
摘要 |
PROBLEM TO BE SOLVED: To provide an interface board for synchronizing the processing of a CPU board on which a CPU is loaded and the processing of a peripheral hardware model obtained by modeling the other peripheral hardware on the computer. SOLUTION: This interface board for connecting a CPU board equipped with at least a CPU to a peripheral hardware simulator for executing the operation of at least one peripheral hardware as a peripheral hardware model is provided with: a standby instruction part for notifying the peripheral hardware model of interruption by receiving interrupt notification from the CPU and making the CPU standby; and a release part for releasing the standby of the CPU which has been put in a standby state by the standby instruction part by receiving the instruction of standby release from the peripheral hardware model which has been notified of the interruption. COPYRIGHT: (C)2009,JPO&INPIT
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申请公布号 |
JP2008282237(A) |
申请公布日期 |
2008.11.20 |
申请号 |
JP20070126314 |
申请日期 |
2007.05.11 |
申请人 |
TOSHIBA CORP;TOSHIBA SOLUTIONS CORP |
发明人 |
ONO TOSHIYUKI;ISHIZUKA AKIRA;ISHII SHIYOUGO |
分类号 |
G06F11/28;G06F13/00 |
主分类号 |
G06F11/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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