发明名称 DECODING CIRCUIT
摘要 Input bits having a predetermined number of bits are divided into a plurality of bits by a bit dividing apparatus. Several of the divided bits are input into a recording apparatus, and are converted into address information. The data subjected to variable length decoding and a number of bits of the data are output from the recording apparatus according to the output of the recording apparatus. A plurality of kinds of variable length decoding are performed by rewriting the table of the recording apparatus.
申请公布号 US2008285658(A1) 申请公布日期 2008.11.20
申请号 US20070946611 申请日期 2007.11.28
申请人 SANYO ELECTRIC CO., LTD.;SANYO SEMICONDUCTOR CO., LTD. 发明人 KOSUGE TETSUO
分类号 H04N7/26 主分类号 H04N7/26
代理机构 代理人
主权项
地址