发明名称 PROCESS FOR FABRICATING SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To enhance reliability of wiring, while preventing the trench width from enlarging in a dual-damascene processing process. SOLUTION: An interlayer insulating film 105 is formed on a first metal wiring 103, and a via hole is made in the interlayer insulating film 105. A first barrier metal 109 is formed on the sidewall inside the via hole, and an organic film is formed in the via hole where the first barrier metal 109 is formed. After etching the organic film to a predetermined position, the first barrier metal 109 exposed by etch back is etched by using the organic film as a mask. Subsequently, the interlayer insulating film 105 is etched to a predetermined position, thus forming a trench. Thereafter, the organic film 110 remaining in the via hole is removed, and a second barrier metal 113 is formed on the first barrier metal 109 in the via hole and on the sidewall of the trench. A second metal wiring 115 is formed in the via hole, where the second barrier metal 113 is formed inside the trench. COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2008282852(A) 申请公布日期 2008.11.20
申请号 JP20070123270 申请日期 2007.05.08
申请人 TOSHIBA CORP 发明人 MATSUMORI HISAKAZU
分类号 H01L21/768;H01L23/522 主分类号 H01L21/768
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