发明名称 |
Formally deriving a minimal clock-gating scheme |
摘要 |
The present invention provides a fully automatic method for obtaining a circuit having minimized power consumption due to clock-gating. A circuit design to be optimized is modified to a reduced power modified design and associated with a clock gating scheme. Verification tools compare the modified design with the original design to a predetermined trigger-events to determine if the modified design can be used. Further modifications may be made iteratively until an optimal design is achieved.
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申请公布号 |
US2008288901(A1) |
申请公布日期 |
2008.11.20 |
申请号 |
US20080107940 |
申请日期 |
2008.04.23 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BAROWSKI HARRY;BUTTS J. ADAM;GEMMEKE TOBIAS;MAEDING NICOLAS;PARUTHI VIRESH |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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