LOW VOLTAGE DATA PATH IN MEMORY ARRAY

摘要

A data path of a memory is from an array (34) of the memory (12), through a sense amplifier (36), through NOR gates (18, 26), through N channel transistors (20, 28), and through a latch (14, 16) that provides an output. The sense amplifier (36) provides complementary data to the NOR gates which provide an output to the N channel transistors (20, 28). The NOR gates (18, 26) provide outputs to the latch (14, 16). This has the affect of providing outputs to gates of one inverter (14) and drains of another inverter (16). Additional P channel transistors (44, 54) are in series with the inverters (14, 16) of the latch. The P channel transistor (44) that is in series with the inverters whose drains are receiving the signal is made to be nonconductive by the output of the NOR gate (26) to block current flow to the N channel transistor (46, 48) that is providing the input to the latch. The blocking of the current reduces the amount of current that the N channel transistor (46, 48) has to sink. This enables the N channel transistor (46, 48), even at a reduced voltage, to be sufficiently conductive to flip the state of the latch.