发明名称 Wafer level package and wafer level packaging method
摘要 Provided are a wafer level package and a wafer level packaging method, which are capable of performing an attaching process at a low temperature and preventing contamination of internal devices. In the wafer level package, a device substrate includes a device region, where a device is formed, and internal pads on the top surface. The internal pads are electrically connected to the device. A cap substrate includes a getter corresponding to the device on the bottom surface. A plurality of sealing/attaching members are provided between the device substrate and the cap substrate to attach the device substrate and the cap substrate and seal the device region and the getter. The sealing/attaching members are formed of polymer. A plurality of vias penetrate the cap substrate and are connected to the internal pads. The getter provided in the sealed space defined by the sealing/attaching members can prevent the devices of the device region from being contaminated by moisture or foreign particles generated during the fabrication process, and the sealing/attaching process can be performed at a lower temperature compared with a typical sealing/attaching process using a metal.
申请公布号 US2008283989(A1) 申请公布日期 2008.11.20
申请号 US20080153373 申请日期 2008.05.16
申请人 SAMSUNG ELECTRO-MECANICS CO., LTD. 发明人 JEUNG WON KYU;CHOI SEOG MOON;HA JOB;PARK SANG HEE;KIM TAE HOON
分类号 H01L23/055;H01L21/54 主分类号 H01L23/055
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