发明名称
摘要 <p>PROBLEM TO BE SOLVED: To provide a packet data processor capable of adding data to a packet without impairing a high speed processing of the packet. SOLUTION: The packet data processor having a packet data processing group to be constituted of a plurality of pipeline structured packet data processing parts each of which performs processing to inputted packets and outputs them to a rear stage respectively is provided with a data adding part provided in a first packet data processing part in the packet data processing group to add data to the inputted packets and a control part to instruct the packet data processing part at the previous stage of the first packet data processing part to stop the output of the packets in order to secure an interval between an object packet to be added and the previous packet at least for data length to be added when the data is added to the inputted packets and to instruct the packet data processing part at the previous stage of the first packet data processing part to restart the output of the packets when the interval with the previous packet is secured.</p>
申请公布号 JP4183920(B2) 申请公布日期 2008.11.19
申请号 JP20010039392 申请日期 2001.02.16
申请人 发明人
分类号 H04L12/773;H04L12/951 主分类号 H04L12/773
代理机构 代理人
主权项
地址