| 摘要 |
A ring oscillator for generating an output signal, comprising a plurality of serially connected main elements for selectively delaying a signal input thereto, each of the plurality of main elements having two circuit paths, a first path including at least one time-delay element for delaying a signal input thereto and a second circuit path bypassing the first circuit path; and a multiplexor (MUX) having a first input coupled to the first circuit path including the at least one time-delay element and a second input coupled to the second circuit path, the MUX selecting the first or second inputs of a plurality of inputs and outputting an output signal. |
