发明名称 Method of designing layout of semiconductor integrated circuit and apparatus for doing the same
摘要 A method of designing a layout of functional blocks and on-chip capacitors in a semiconductor integrated circuit, includes the steps of, in sequence, (a) placing a functional block, (b) placing an on-chip capacitor in an area which remains vacant after the step (a) has been carried out, (c) overlapping a portion of the functional block having been placed in the step (a) and a portion of the on-chip capacitor having been placed in the step (b) each other, if possible, and (d) placing an on-chip capacitor in a vacant area caused by carrying out the step (c).
申请公布号 US7454734(B2) 申请公布日期 2008.11.18
申请号 US20060376178 申请日期 2006.03.16
申请人 NEC CORPORATION 发明人 UCHIDA KOHEI
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
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