| 摘要 |
A pipe latch control circuit of semiconductor memory apparatus is provided to realize high speed operation by using an operation speed identification signal. In a pipe latch control circuit of semiconductor memory apparatus, a pipe latch pulse signal generation unit(100) receives a pipe control signal, generates delay signal(DLY) in response to operation speed identification signal, generates a pipe latch signal, which is disable when the delay signal is transited corresponding to timing when the pipe control signal is enabled. A pulse control unit(200) generates operation speed identification signal to control the designated time. |
