发明名称 ACCELERATING MODEL CHECKING VIA SYNCHRONY
摘要 A system and method for program verification by model checking in concurrent programs includes modeling each of a plurality of program threads as a circuit model, and generating a full circuit for an entire program by combining the circuit models including constraints which enforce synchronous execution of the program threads. The program is verified using the synchronous execution to reduce an amount of memory needed to verify the program and a number of steps taken to uncover an error.
申请公布号 US2008282221(A1) 申请公布日期 2008.11.13
申请号 US20080054575 申请日期 2008.03.25
申请人 NEC LABORATORIES AMERICA, INC. 发明人 KAHLON VINEET;GUPTA AARTI
分类号 G06F9/44 主分类号 G06F9/44
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