| 摘要 |
Additional transistors P 1 and P 2 which are PMOS transistors are connected to load transistors PL 1 and PL 2 which are PMOS transistors such that drain electrodes of the additional transistors P 1 and P 2 and drain electrodes of the load transistors PL 1 and PL 2 are connected at a node 1 and a node 2 while gate electrodes of the additional transistors P 1 and P 2 and gate electrodes of the load transistors PL 1 and PL 2 are connected at the node 1 and the node 2 . A source electrode of the additional transistor P 1 is connected to an additional transistor control circuit, which is provided for each column. The additional transistor control circuit sets control signals S 1 and S 2 to the H level in other times than data write so that the additional transistor P 1 or P 2 compensates the load transistor PL 1 or PL 2 , thereby increasing the static margin. In data write, the additional transistor control circuit sets the control signals S 1 and S 2 to the low level, thereby preventing the additional transistors from hindering the data write, and thus increasing the write margin.
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