| 摘要 |
PROBLEM TO BE SOLVED: To solve the problem that it is necessary to repeat shifts, and launches and captures equal to the number of clock systems to cause a prolonged test time when a pass exists between a plurality of clock domains of asynchronous clocks. SOLUTION: The semiconductor test circuit includes a plurality of clock control circuits corresponding to the plurality of the clock domains which has the (n) th clock control circuit for outputting the (n) th clock for a delay test to the (n) th scan chain circuit connected to the (n) th clock domain operating in synchronization with the (n) th clock based on the (n) th scan enable signal, and the (n+1) th control circuit for outputting the (n+1) th clock for a delay test to the (n+1) th scan chain circuit connected to the (n+1) th clock domain operating in synchronization with the (n+1) clock asynchronous with the (n) th clock based on the (n+1) th scan enable signal output from the (n) th clock control circuit based on an end of output of the (n) th clock for a delay test. COPYRIGHT: (C)2009,JPO&INPIT
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