发明名称 TEST CIRCUIT FOR PERFORMING MULTIPLE TEST MODES
摘要 A test circuit includes a first reset pulse generator configured to generate a first reset pulse when a test mode is performed or when power is up, a test mode maintenance signal generator configured to provide a test mode maintenance signal activated in response to a predetermined consecutive test information data, the activation of the test mode maintenance signal being controlled by the first reset pulse, a second reset pulse generator configured to generate a second reset pulse when the test information data is received as a predetermined test mode reset data or when power is up, and a test mode selection signal generator configured to receive the test information data provided from the test mode maintenance signal generator and the test mode maintenance signal and to generate a specific test mode selection signal, the activation of the specific test mode selection signal being controlled by the second reset pulse.
申请公布号 US2008278189(A1) 申请公布日期 2008.11.13
申请号 US20070959392 申请日期 2007.12.18
申请人 HYNIX SEMICONDUCTOR INC. 发明人 HUR YOUNG DO
分类号 G01R31/02 主分类号 G01R31/02
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