| 摘要 |
Techniques pertaining to designs of ElectroStatic Discharge (ESD) protection circuits are disclosed. In one embodiment, an ESD protection circuit combines a substrate-driving technique with a gate-driving technique to ease the ESD design and save the silicon area. In another embodiment, an ESD protection circuit is based on a Positive Metal Oxide Semiconductor field effect transistor (PMOS) in a standard Complementary Metal Oxide Semiconductor (CMOS) process. In another embodiment, the ESD protection circuit is based on a negative Metal Oxide Semiconductor field effect transistor (NMOS) in the standard CMOS process. Depending on implementation, the ESD protection circuit is implemented for a negative voltage input pin, a normal input pin, and a power supply clamp circuit.
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