| 摘要 |
PROBLEM TO BE SOLVED: To provide a memory access control device for reducing memory access latency of access from a specified memory master in a unified memory architecture and a system of a multiprocessor. SOLUTION: The device includes an arbiter 20 and an sub-arbiter 30 receiving access requests from a plurality of memory masters 11-14 to arbitrate the requests; a memory controller 40; and a memory 50 comprising a plurality of banks. When the bank of a memory to be used by an access request which has been permitted by the arbiter 20 and currently under execution differs from the bank of a memory to which the access request from the sub-arbiter 30 intends to access, and a kind of the access request which has been permitted by the arbiter 20 and currently under execution is the same as a kind of memory access which is intended to perform by the sub-arbiter 30, the device determines that an access efficiency does not deteriorate, suspends the memory access by the arbiter 20, and makes interruption with the memory access by the sub-arbiter 30. COPYRIGHT: (C)2009,JPO&INPIT
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