SPLIT GATE MEMORY CELL IN A FINFET

摘要

A memory cell is implemented using a semiconductor fin (105, 107) in which the channel region is along a sidewall of the fin between source and drains regions. One portion of the channel region has a select gate (731) adjacent to it and another other portion has the control gate (1001) adjacent to it with a charge storage structure there between. In some embodiments, independent control gate structures are located adjacent opposite sidewalls of the fin so as to implement two memory cells.