发明名称 Low redundancy data RAM architecture for monolithic time-space switches
摘要 A non-blocking time and space switch is provided, based on specific memory method functions, called replica representatives, which shows a much lower data redundancy compared with the common RAM based approach as a consequence of multiple replica representatives. This allows the monolithic implementation of high through put time space switches.
申请公布号 US7450575(B2) 申请公布日期 2008.11.11
申请号 US20050058409 申请日期 2005.02.16
申请人 NEC ELECTRONICS CORPORATION 发明人 TOSCHI VALENTINO
分类号 H04J3/00;H04Q11/00;H04Q11/04 主分类号 H04J3/00
代理机构 代理人
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