发明名称 Asynchronous signal input apparatus and sampling frequency conversion apparatus
摘要 In an asynchronous data input apparatus, a writing section writes data successively into a FIFO buffer memory at an variable input rate so that the data are accumulated in the FIFO buffer memory. A reading section reads the accumulated data successively from the FIFO buffer memory at an variable output rate so that the data amount residing in the FIFO buffer memory varies temporally. A detector detects a current data amount residing in the FIFO buffer memory, and a current direction of variation of the data amount residing in the FIFO buffer memory. A loop filter generates control information according to both of the detected current data amount and the detected current direction of variation of the data amount. A controller regulates the output rate according to the control information so as to promptly converge the current data amount residing in the FIFO buffer memory to a target data amount.
申请公布号 US7450678(B2) 申请公布日期 2008.11.11
申请号 US20040999884 申请日期 2004.11.30
申请人 YAMAHA CORPORATION 发明人 NISHIOKA NAOTOSHI
分类号 H03H17/00;H04L7/00;G06F15/00;H03H17/02;H03H17/06;H04L25/00;H04L25/40 主分类号 H03H17/00
代理机构 代理人
主权项
地址