MULTI-FREQUENCY DEBUG NETWORK FOR A MULTIPROCESSOR ARRAY
摘要
A debug network on a multiprocessor array having multiple clock domains includes a backbone communication channel which communicates with information nodes on the channel. The information nodes store and access information about an attached processor. The nodes are also coupled to registers within the attached processor, which operate at the speed of the processor. A master controller solicits information from the information nodes by sending messages along the backbone. If a message requires interaction with a processor register, the node performs the action by synchronizing to the local processor clock.
申请公布号
WO2008024697(A3)
申请公布日期
2008.11.06
申请号
WO2007US76278
申请日期
2007.08.20
申请人
AMBRIC, INC.;JONES, ANTHONY, MARK;WASSON, PAUL, M.;WHITE, EDMUND, H.
发明人
JONES, ANTHONY, MARK;WASSON, PAUL, M.;WHITE, EDMUND, H.