发明名称 METHOD FOR PERFORMING FAILURE MODE AND EFFECTS ANALYSIS OF AN INTEGRATED CIRCUIT AND COMPUTER PROGRAM PRODUCT THEREFOR
摘要 A method for performing failure mode and effects analysis (FMEA) on integrated circuits including preparing a FMEA database of an integrated circuit under design and computing FMEA results from the FMEA database. Information is automatically extracted from an integrated circuit description. The extraction of information includes reading integrated circuit information, partitioning the circuit in invariant and elementary sensitive zones (SZ), using the information in the preparation step of a FMEA database. Optionally a FMEA validation stage may be performed with which FMEA computed results are compared with FMEA measured results to obtain FMEA validated results.
申请公布号 US2008276206(A1) 申请公布日期 2008.11.06
申请号 US20080101585 申请日期 2008.04.11
申请人 YOGITECH S.P.A. 发明人 MARIANI RICCARDO
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
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