SEMICONDUCTOR MEMORY

摘要

Provided is a semiconductor memory by which a time required for bringing a source voltage and a drain voltage of a clamping transistor into a steady state can be shortened. The semiconductor memory includes a memory cell (11), which includes a storage element (11b) wherein a resistance value changes by storage information; a bit line (2) connected to the memory cell (11); and a current detecting means (4), which applies a discretionary voltage to the bit line (2) to permit a current to flow in the memory cell (11) and detects the current. The current detecting means (4) includes an inverting amplifier means (41) for inverting and amplifying the potential of the bit line (2); a detecting load means (42) connected to a power supply; a clamping transistor (M1) wherein a gate receives output from the inverting amplifier means (41), a drain receives a current from the power supply through the detecting load means (42), a source applies a discretionary potential to the bit line (2) and supplies the memory cell (11) with a current; and a current supply means (M2) which supplies the drain with an auxiliary current until the source voltage and the drain voltage of the clamping transistor (M1) are brought into the steady state, and stops supply of the auxiliary current when the voltages are in the steady state.