PHASE-LOCKED LOOP CIRCUIT AND METHOD

摘要

A phase-locked loop circuit having a dual-reference input and a phase detector. The dual-reference input is to accept both a rising edge of an input clock having a first phase and a falling edge of the input clock having a second phase. The phase detector is coupled to the dual-reference input and is to produce a center phase signal based upon and centered in phase between the first and second phases. The phase detector also comprise a feedback loop to adjust tracking error and provide a tracking output signal. Other apparatus embodiments and methods of operating the circuits are also disclosed.