| 摘要 |
PROBLEM TO BE SOLVED: To provide a method, device and program for designing a semiconductor integrated circuit, capable of reducing the time required for determination and correction of error in LRC (lithography rule check). SOLUTION: The method for designing a semiconductor integrated circuit using the design device having an arithmetic part and a storage part comprises processes in which the arithmetic part generates electric filter graphic data 34 and electric filter data 35 using circuit diagram data 31 and a statistic timing analysis result 30 and stores the data in the storage part; the arithmetic part generates design data by use of the electric filter graphic data to create a layout pattern; the arithmetic part performs lithographic simulation to the layout pattern to detect a lithographic error; the arithmetic part determines whether the error is an error needing correction or not in consideration of electric characteristics by use of the electric filter database; and the arithmetic part performs, when the error is the error needing correction as the result of determination, correction of the layout. COPYRIGHT: (C)2009,JPO&INPIT
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