METHOD FOR GENERATING ERRONEOUS TEST-AVOIDING TYPE TEST INPUT IN 2-PATTERN TEST OF SEMICONDUCTOR INTEGRATED CIRCUIT

摘要

Provided is a test input generation device which applies a test input to a semiconductor integrated circuit (10) and compares expected values of response so as to judge whether a combined circuit unit (17) has failed. The method includes: a first step which decides a test pattern containing a logic value which can judge whether a failure is present and a undefined value; a second step which selects critical paths (19, 19a, 19b) formed when the test pattern is applied; a third step which identifies critical gates of the critical paths (19, 19a, 19b); and a fourth step which decides the undefined value so as to reduce the number of state changes indicating the number of critical gates having a changing gate state. Thus, it is possible to prevent a delay of output from the critical paths (19, 19a, 19b) and avoid an erroneous test by reducing the number of state changes.