UNIFIED MEMORY ACHITECTURE AND DISPLAY CONTROLLER TO PREVENT DATA FEED UNDER-RUN

摘要

A display controller for controlling data in an isochronous display where fluctuation of data feed latency occurs, the display controller including an input memory (204) which receives pixel data, and transmits the pixel data through a main route (208) and a secondary route (210). Pixel data transmitted through the main route is processed for delivery to the display in a predetermined manner. The secondary route (224, 228, 230, 234) comprises a memory (228, 230) for storing a two-dimensional section of the pixel data that corresponds at least in part to the pixel data being transmitted through the main route at that time and a detector for identifying a data feed latency event. In response to the event the transmission of the pixel data is switched to the secondary route and the pixel data having been processed, is transmitted through the secondary route for delivery to the display such that when a data feed latency event occurs the stored two-dimensional section of the pixel data from the secondary route is displayed on the display.