发明名称 TEST CIRCUIT, PATTERN GENERATION SYSTEM, AND PATTERN GENERATION METHOD
摘要 PROBLEM TO BE SOLVED: To solve such a problem that it has conventionally been impossible to reduce the amount of data that is input to and output from a semiconductor integrated circuit. SOLUTION: A test circuit 1 connected between a test target circuit 2 and a plurality of external terminals 3a to 3g includes: N first holding circuits 6a to 6d respectively holding N unit patterns produced by dividing an internal signal pattern to be input to or output from the test target circuit 30 by N, where N is a natural number of two or greater; and a control circuit that causes the internal signal pattern held in the N first holding circuits 6a to 6d to be changed selectively on a unit pattern basis based on an identification signal assigned to each of the unit patterns beforehand, or that causes the internal signal pattern held in the N first holding circuits 6a to 6d to be output selectively on a unit pattern basis based on the identification signal. COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2008268185(A) 申请公布日期 2008.11.06
申请号 JP20080046319 申请日期 2008.02.27
申请人 NEC ELECTRONICS CORP 发明人 SASAKI YASUO
分类号 G01R31/28;G01R31/3183 主分类号 G01R31/28
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