发明名称
摘要 Encoding-system includes a check-bit-generation-unit configured to generate N-ary-parity-bits by processing information composed of N-ary-symbols (where N is a power of 2) in modulo-N with a LDPC-matrix composed of binary elements, an encoded-sequence-generation-unit configured to generate an encoded sequence including the information composed of the N-ary-symbols and the N-ary-parity-bits, a modulation unit configured to modulate the encoded sequence in a modulation scheme having N-ary-modulation-symbols to produce a modulated signal, a demodulation-unit configured to demodulate the modulated signal to produce a demodulated signal, a metric-generation-unit configured to generate a metric for each of N-modulation-signal-points from the demodulated signal to obtain a plurality of metrics, and a decoding-unit configured to decode the encoded sequence by obtaining posteriori probabilities of the symbols in accordance with a state transition having an N-state defined by a binary LDPC-matrix corresponding to the LDPC-encoder encoding the encoded sequence, on the basis of the metrics.
申请公布号 JP4177824(B2) 申请公布日期 2008.11.05
申请号 JP20050075933 申请日期 2005.03.16
申请人 发明人
分类号 H03M13/19;H04L27/36;H04L27/38 主分类号 H03M13/19
代理机构 代理人
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