| 摘要 |
A dual data rate (DDR) output circuit has first and second data paths therein that are asymmetric. The first data path is provided through a single-stage latch unit and the second data path is provided through a dual-stage flip-flop device containing a cascaded arrangement of two latch units. The DDR output circuit includes a latch unit, a flip-flop and a buffer circuit. The latch unit is configured to latch-in first data in-sync with a first edge of a clock signal and the flip-flop is configured to latch-in second data in-sync with the first edge of the clock signal. A buffer circuit is also provided. The buffer circuit is electrically coupled to an output of the latch unit and an output of the flip-flop. The buffer circuit is configured to generate the first data at an output terminal of the DDR output circuit in-sync with one edge (e.g. rising or falling) of the clock signal and further configured to generate the second data at the output terminal in-sync with another edge (e.g., falling or rising) of the clock signal.
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