发明名称 |
Mass memory device and method for operating a mass memory device |
摘要 |
A mass memory device ( 1 ) having a plurality of mass memories ( 2 ) and having at least two bridge controllers ( 3 ) which are coupled to the mass memories ( 2 ) by a data bus. A first common cache memory unit ( 4 ) is provided, to which the bridge controllers ( 3 ) are connected by means of an additional cache synchronization system for the purpose of storing and synchronizing data which are to be stored. A method is provided for operating a mass memory device ( 1 ) having a plurality of mass memories ( 2 ) and having at least two bridge controllers ( 3 ) which can be used to address the mass memories ( 2 ), and at least one first common first common cache memory unit ( 4 ) which is associated with the bridge controllers ( 3 ). All data to be stored are initially stored on the first common cache memory unit ( 4 ) and are automatically mirrored on an optional further common cache memory unit ( 4 ). The data initially stored in the first common cache memory unit ( 4 ) are transferred to the mass memories ( 2 ) for storage therein.
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申请公布号 |
US7447842(B2) |
申请公布日期 |
2008.11.04 |
申请号 |
US20040872683 |
申请日期 |
2004.06.21 |
申请人 |
FUJITSU SIEMENS COMPUTERS GMBH |
发明人 |
DEPTA ROBERT |
分类号 |
G06F12/00;G06F3/06;G06F12/08 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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