发明名称 |
Multi-layer spacer with inhibited recess/undercut and method for fabrication thereof |
摘要 |
A semiconductor structure includes a multi-layer spacer located adjacent and adjoining a sidewall of a topographic feature within the semiconductor structure. The multi-layer spacer includes a first spacer sub-layer comprising a deposited silicon oxide material laminated to a second spacer sub-layer comprising a material that is other than the deposited silicon oxide material. The first spacer sub-layer is recessed with respect to the second spacer sub-layer by a recess distance of no greater than a thickness of the first spacer sub-layer (and preferably from about 50 to about 150 angstroms). Such a recess distance is realized through use of a chemical oxide removal (COR) etchant that is self limiting for the deposited silicon oxide material with respect to a thermally grown silicon oxide material. Dimensional integrity and delamination avoidance is thus assured for the multi-layer spacer layer.
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申请公布号 |
US7446007(B2) |
申请公布日期 |
2008.11.04 |
申请号 |
US20060560893 |
申请日期 |
2006.11.17 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
ADKISSON JAMES W.;CANTELL MARC W.;ELLIOTT JAMES R.;HART, III JAMES V.;MARTIN DALE W. |
分类号 |
H01L21/336 |
主分类号 |
H01L21/336 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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